1. Field of the Invention
The present invention relates to a semiconductor integrated circuit incorporating a test circuit for mass production tests (referred to as a board test hereinafter) of printed circuit boards with semiconductor and other devices mounted thereon.
2. Description of the Prior Art
The quantity of functions incorporated into a circuit board has been dramatically increased due to the recent advancement of semiconductor technology. It is accordingly most important for a semiconductor integrated circuit mounted onto the board to be suitably designed for the board test in order to secure the quality of the mass-produced board. One representative technique therefor is the boundary scan employed as IEEE standard 1149.1-1990 "IEEE Standard Test Access Port and Boundary-Scan Architecture" (refer to "Simplification of Board Test by Boundary Scan" by Peter Hansen, et al. in Nikkei Electronics dated Jan. 8, 1990, No. 490, pp. 301-7).
Hereinbelow, one example of the semiconductor integrated circuit incorporating the aforementioned boundary scan test circuit will be depicted with reference to FIG. 4.
FIG. 4 is a block diagram of a board mounted with a conventional semiconductor integrated circuit. In FIG. 4, reference numerals denote respectively: 401 a board, 402, 403 integrated circuits A, B mounted on the board 401, 404 a digital signal input terminal of the integrated circuit A402, 405 a digital signal output terminal of the integrated circuit A402, 406 a digital signal input terminal of the integrated circuit B403 the terminal being connected to the digital signal output terminal 405, 407 a digital signal output terminal of the integrated circuit B403, 408 a digital signal input terminal of the board 401, the terminal being connected to the digital signal input terminal 404 of the integrated circuit A402, 409 a digital signal output terminal of the board 401 and connected to the digital signal output terminal 407 of the integrated circuit B403, 410 a test switching terminal connected in common to the integrated circuits A402 and B403, 411 a test signal input terminal of the board 401, 412 a test signal output terminal of the board 401, 413 a boundary scan input circuit, 414 a boundary scan output circuit, 415 a test signal output terminal of the integrated circuit A402, and 416 a test signal input terminal of the integrated circuit B403.
The operation of the board mounted with the conventional semiconductor integrated circuits in the structure as above will be discussed now hereinbelow.
When the test switching terminal 410 is set for the normal operation mode, the boundary scan input circuit 413 of the integrated circuit A402 operates as a normal digital signal input circuit, taking a signal through the digital signal input terminal 408 into the integrated circuit A402. On the other hand, the boundary scan output circuit 414 of the integrated circuit A402 works as a normal digital signal output circuit, by outputting a signal through the digital signal output terminal 405 to the digital signal input terminal 406 of the integrated circuit B403. The integrated circuit B403 operates in the same manner as the integrated circuit A402. Therefore, the signal input through the digital signal input terminal 408 is, on the whole of the board, processed in the integrated circuits A402 and B403 and is outputted to the digital signal output terminal 409. If the mass production quality of the board 401, that is, whether all the input/output terminals of the integrated circuits A402 and B403 are perfectly soldered, is to be confirmed in this state, a signal output to the digital signal output terminal 409, when a complicated test data is input through the digital signal input terminal 408, should be compared with an expected value. According to this method, however, it is necessary to know the input/output response of the integrated circuits A402 and B403 during the normal operation beforehand, and moreover, it is difficult to specify which of the terminals is improperly connected in the case where the expected value is not obtained. The boundary scan test circuit has been devised to solve the aforementioned disadvantages.
When the test switching terminal 410 is set for the test mode, the boundary scan input circuit 413 and the boundary scan output circuit 414 operate as shift registers connected in series. In other words, the signal input through the test signal input terminal 411 is, after going through the input/output circuit of the integrated circuit A402, outputted to the test signal output terminal 415 of the integrated circuit A402. The signal at the test signal output terminal 415 is input to the test signal input terminal 416 of the integrated circuit B403, and output to the test signal output terminal 412 of the board 401 after going through input/output circuit of the integrated circuit B403.
The board 401 will be checked in a manner as described below.
(1) After the test switching terminal 410 is set to the test mode, a signal to set a desired data in the digital signal output terminals 405 and 407 of the integrated circuits A402 and B403 is input through the test signal input terminal 411. The value of the digital signal output terminal 409 is first checked.
(2) Then, the test switching terminal 410 is set to the normal operation mode and the signal from the digital signal input terminal 408 is taken inside through the digital signal input terminal 404 of the integrated circuit A402. The resulting signal from the digital signal output terminal 405 is taken into the integrated circuit B403 through the test signal input terminal 406.
(3) The test switching terminal 410 is switched to the test mode again. The data taken into the integrated circuits A402 and B403 in the above step (2) is taken outside through the test signal input terminal 412 in series and the value is checked.
In the above-described procedure, it is possible to inspect the board 401 without knowing the function of the normal operation of the integrated circuits A402 and B403.
Now, the integrated circuits A402 and B403 will be described more in detail with reference to FIG. 5. FIG. 5 is a block diagram indicating the internal structure of the conventional semiconductor integrated circuit, in which reference numerals respectively designate: 501 an integrated circuit, 502 to 504 digital signal input terminals (DI), 505 to 507 digital signal output terminals (DO), 508 a test switching terminal (TS), 509 a test signal input terminal (TI), 510 a test signal output terminal (TO), 511 to 513 boundary scan input circuits (CI), and 515 to 517 boundary scan output circuits (CO). Each of the boundary scan input and output circuits 511 to 513 and 515 to 517 has a digital signal input terminal D, a clock input terminal CK, a digital signal output terminal Q, a test switching terminal TS, a test signal input terminal TI, and a test signal output terminal TO. A digital circuit 514 performs the original function of the integrated circuit 501. The semiconductor integrated circuit of the above structure operates in a manner as follows.
When the test switching terminal 508 is set to the normal mode, the boundary scan input circuits 511 to 513 and the boundary scan output circuits 515 to 517 serve as flip-flops, so that an input through D is output to Q and TO. Therefore, the integrated circuit 501 functions normally. Meanwhile, when the test switching terminal 508 is set for the test mode, the boundary scan input circuits 511 to 513 work as flip-flops to input a signal from TI and output the same to TO, while the boundary scan output circuits 515 to 517 work as flip-flops to have a TI input and Q and TO outputs. The TO output of the boundary scan input circuit 513 is connected to the TI input of the boundary scan output circuit 517. Accordingly, the digital signal input through the test signal input terminal 509 of the integrated circuit 501 is, after passing through the six flip-flops, outputted to the test signal output terminal 510. The operation depicted with reference to FIG. 4 is thus realized.
The internal structure of the boundary scan input circuits (CI) 511 to 513 and boundary scan output circuits (CO) 515 to 517 will be described by way of example with reference to FIGS. 6 and 7.
FIG. 6 is a circuit diagram inside the boundary scan input circuit within the conventional semiconductor integrated circuit shown in FIG. 5, in which reference numerals denote respectively: 601 a digital signal input terminal (D), 602 a clock input terminal (CK), 603 a digital signal output terminal (Q), 604 a test switching terminal (TS), 605 a test signal input terminal (TI), 606 a test signal output terminal (TO), 607 and 608 flip-flops, and 609 a digital signal switching device.
The boundary scan input circuit in the above structure operates as described hereinbelow.
With the test switching terminal 604 set to the normal mode, the digital signal switching device 609 is connected to the side of the digital signal input terminal 601. A data input terminal of the flip-flop 608 is connected to the output terminal of the digital signal switching device 609. Therefore, when a clock signal is fed to the clock input terminal 602, the data at the digital signal input terminal 601 is outputted to the digital signal output terminal 603 and the test signal output terminal 606. If the test switching terminal 604 is switched to the test mode, the digital signal switching device 609 is connected to the side of the test signal input terminal 605, so that the data at the digital signal input terminal 601 is outputted to the digital signal output terminal 603 and the data at the test signal input terminal 605 is outputted to the test signal output terminal 606.
FIG. 7 illustrates an example of a circuit diagram inside the boundary scan output circuit of the conventional semiconductor integrated circuit of FIG. 5. In FIG. 7, reference numerals indicate respectively: 701 a digital signal input terminal (D), 702 a clock input terminal (CK), 703 a digital signal output terminal (Q), 704 a test switching terminal (TS), 705 a test signal input terminal (TI), 706 a test signal output terminal (TO), 707 and 708 flip-flops, and 709 a digital signal switching device.
The operation of the above boundary scan output circuit will be explained below.
When the test switching terminal 704 is set to the normal mode, the digital signal switching device 709 is connected to the side of the digital signal input terminal 701. Since the data inputs at the flip-flops 708 and 707 are both connected to an output of the digital signal switching device 709, the data at the digital signal input terminal 701 is outputted to the digital signal output terminal 703 and the test signal output terminal 706 when a clock signal is added to the clock input terminal 702. If the test switching terminal 704 is in the test mode, the digital signal switching device 709 is connected to the side of the test signal input terminal 705, and the data at the test signal input terminal 705 is outputted to the digital signal output terminal 703 and the test signal output terminal 706.
The operation discussed with reference to FIG. 5 is realized by the above-described boundary scan input/output circuits.
In the foregoing prior art, all the semiconductor integrated circuits on the board are supposed to be constituted of digital circuits. However, particularly in the case of processing video signals, there may often be mounted both analog circuits and digital circuits on the same board, and thus the boundary scan method cannot meet the board test.